1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device having an n-type FET and a p-type FET. The present invention also relates to such a semiconductor device.
2. Related Art
A conventional semiconductor device that has an n-type FET and a p-type FET is disclosed in Japanese Laid-open patent publication No. 2004-349372. The semiconductor device disclosed in the document is shown in FIG. 20. This semiconductor device 100 includes an n-type FET forming region having an n-type FET 102 formed on a semiconductor substrate 112, and a p-type FET forming region having a p-type FET 104 formed on the semiconductor substrate 112. In the drawings, “nFET” indicates the “n-type FET forming region” in which the n-type FET is to be formed or has already been formed. Also, “pFET” indicates the “p-type FET forming region” in which the p-type FET is to be formed or has already been formed. The n-type FET forming region and the p-type FET forming region are separated from each other by a device isolation layer 114 formed by STI (Shallow Trench Isolation) in the semiconductor substrate 112.
In the n-type FET forming region, a p-type well 112a is formed in the semiconductor substrate 112. Further, n−-type first source/drain extension regions (hereinafter referred to as the first extension regions) 140 and n+-type first source/drain regions 142 are formed in surface regions of the p-type well 112a. A first gate oxide film 116 and a first gate electrode 118 are stacked on the surface of the semiconductor substrate 112. A first silicide layer 120 is formed on the top layer of the first gate electrode 118. First insulating films 122 are formed on the sidewalls of the first gate oxide film 116 and the first gate electrode 118. Sidewall insulating films 124 are formed on the outer surfaces of the first insulating films 122. The first insulating films 122 and the sidewall insulating films 124 constitute first sidewalls 126.
In the p-type FET forming region, an n-type well 112b is formed in the semiconductor substrate 112. Further, p−-type second source/drain extension regions (hereinafter referred to as the second extension regions) 150 and p+-type second source/drain regions 152 are formed in surface regions of the n-type well 112b. A second gate oxide film 130 and a second gate electrode 132 are stacked on the surface of the semiconductor substrate 112. A second silicide layer 134 is formed on the top layer of the second gate electrode 132. First insulating films 122 and second insulating films 123 are stacked in this order on the side walls of the second gate oxide film 130 and the second gate electrode 132. Sidewall insulating films 124 are formed on the outer surfaces of the second insulating films 123. The first insulating films 122, the second insulating films 123, and the sidewall insulating films 124 constitute second sidewalls 136. Further, a stopper layer 138 is formed so as to cover all those regions.
A method of manufacturing the semiconductor device 100 is now described with reference to the accompanying drawings. FIGS. 21A through 23G are process cross-sectional views illustrating the method of manufacturing the semiconductor device 100.
First, the semiconductor substrate 112 that has the p-type well 112a and the n-type well 112b separated by the device isolation layer 114 is prepared. In the n-type FET forming region, the first gate oxide film 116 and the first gate electrode 118 are stacked in this order on the semiconductor substrate 112. In the p-type FET forming region, the second gate oxide film 130 and the second gate electrode 132 are stacked in this order on the semiconductor substrate 112. The first silicide layer 120 is formed on the top layer of the first gate electrode 118, and the second silicide layer 134 is formed on the top layer of the second gate electrode 132. The first insulating film 122 and the second insulating film 123 are stacked in this order so as to cover the n-type FET forming region and the p-type FET forming region (FIG. 21A).
Next, the p-type FET forming region is covered with a resist film 160. The resist film 160 is patterned so as to open the n-type FET forming region. Predetermined etching is then performed in the n-type FET forming region. Through the etching, the first insulating film 122 and the second insulating film 123 are removed from the first silicide layer 120 and from the surface of the semiconductor substrate 112. The second insulating film 123 is further removed from the side walls of the first gate electrode 118, so that only the first insulating film 122 is left on the side walls of the first gate electrode 118 (FIG. 21B).
Ion implantation is then performed through the exposed surface of the semiconductor substrate 112, so as to form the first extension regions 140 that serve as electric connecting portions between the channel regions and the first source/drain regions 142 described later in surface layer of P type well 112a (FIG. 22C).
Next, the n-type FET forming region is covered with a resist film 162. The resist film 162 is patterned so as to open the p-type FET forming region. In the p-type FET forming region, the first insulating film 122 and the second insulating film 123 are removed formed on the surface of the semiconductor substrate 112 by etching or the like, so that the surface of the semiconductor substrate 112 is exposed (FIG. 22D)
Ion implantation is then performed through the exposed surface of the semiconductor substrate 112, so as to form the second extension regions 150 that serve as electric connecting portions between the channel regions and the second source/drain regions 152 described later in surface layer of N type well 112b (FIG. 23E).
After the resist film 162 is removed, an insulating film (not shown) is formed so as to cover those regions, and etchback is performed. The first sidewalls 126 are then formed on the side walls of the first gate oxide film 116 and the first gate electrode 118, and the second sidewalls 136 are formed on the side walls of the second gate oxide film 130 and the second gate electrode 132 (FIG. 23F). The stopper layer 138 is then formed so as to cover the n-type FET forming region and the p-type FET forming region. Thus, the semiconductor device 100 having the n-type FET 102 and the p-type FET 104 is completed (FIG. 23G).
In the semiconductor device disclosed in the above-described document, however, there is room for improvement. In the n-type FET 102, the first insulating films 122 are formed only on the side walls of the first gate electrode 118, and the surface of the semiconductor substrate 112 is exposed. Because of this, the surface regions of the substrate in which the first extension regions 140 are formed deteriorate during the procedures for removing the resist film and forming the sidewalls. As a result, the characteristics of the n-type FET are degraded.
On the other hand, the method of manufacturing the semiconductor device disclosed in the above-described document also has room for improvement. In the n-type FET forming region in the semiconductor substrate 112, the surface regions of the substrate in which the first extension regions 140 are formed are not protected, when the resist film 160 is removed in the p-type FET forming region (FIGS. 22C and 22D). In the n-type FET forming region in the semiconductor substrate 112, the resist film 162 formed directly on the substrate surfaces in which the first extension regions 140 are formed is removed (FIGS. 23E and 23F). During the procedures for removing the resist films, the substrate surface layers in which the first extension regions 140 are formed tend to deteriorate, resulting in degradation of the characteristics of the n-type FET 102.
The degradation of the characteristics of an n-type FET causes a variation in performance of a semiconductor device. As the diffusion in the first extension regions has been becoming shallower these days, the condition of the surface of the semiconductor substrate greatly affects the characteristics of the n-type FET. Therefore, when the surface of the semiconductor substrate deteriorates, the characteristics of the n-type FET are even more degraded. With this situation being taken into consideration, degradation of the characteristics of the n-type FET should be restrained, so that a short-channel effect in the n-type FET forming region can be restrained and the characteristics of the n-type FET can be improved.